As shown in Figure 40, RICH FEE consisted of 15 modules in 9U VME compatible crate, one Controller Modules, ten AMU/ADC Modules, two LVL1 Trigger Modules, and two Readout Modules. A Controller Module was placed in the center of crate, other modules were placed symmetrically in left and right. The brief description about these modules are presented below.
The Controller Module is a central processing unit of RICH FEE. Other modules were initialized and configured thorough this module. The configuration data were transmitted from online control system via ARCNET. Also, this module was connected to Master Timing Module via G-LINK fiber and received the timing information and the control signal. The timing signal was sent to the AMU/ADC module via Category-5 twisted pair cable.
The AMU/ADC module received the output from the pre amplifier, and recorded informations of timing and charge of the signal in an analog memory. When it was triggered, these information were digitized and sent to the Read out module. To achieve this process, the AMU/ADC Module had two kinds of ASIC chip. The one was the Integrater (Int-R) chip which had 8 channels of integraters and Time to Analog converter. The other was AMU/ADC (Analog Memory Unit/A-D Converter) chip which was comprising of 32 channels of 64 analog memory units and 12 bits A-D converters. Both chips was developed at Oak Ridge National Laboratory. One AMU/ADC Module had 8 Int-R chips and the number of channel in one module was 64. The analog memory hold an integrated charge and timing information at each bunch crossing. Once the trigger signal was received, memorized data corresponding to the trigger were converted to digital data and were sent to the Readout module. Each Readout Module collected data from 5 AMU/ADC Modules via two separated bus(32 bit each) in backplane. The collected data were sent to DCM via G-LINK.
The Int-R chip was the complex of several circuits, which is shown in Fig. 41.
For the charge measurement, it had charge integrater and Variable Gain Amplifier (VGA). For the timing measurement, it had Leading Edge Discriminater, Constant Fraction Discriminater, and Time to Amplitude Converter (TAC). Also, it had 2 Trigger Sum circuit, calibration circuit and various Digital to Analog Converters.
The maximum outputs of both VGA and TAC were adjusted to be 3.25V that matched the input dynamic range of AMU/ADC chips. The eight bit ADC resolution which corresponds to 500ps was required for TAC. As shown in Fig. 42, the charge information was given by